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HV9980
Features

3-Channel LED Array Driver IC
Integrated 200V, 25 (typ.) MOSFETs Programmable output current to 80mA per channel TTL compatible PWM dimming inputs 3-Phase synchronous operation Leading edge blanking Short circuit protection with skip mode Over-temperature protection
illumination. The output currents are programmed by controlling peak source current in each of the three internal 200V, 25 switching MOSFETs. The peak current is detected by monitoring voltage at external sense resistors connected to RSENSE1-3. The switching MOSFET is turned off when the corresponding current sense signal exceeds the reference voltage applied at REF1-3 (in the case of normal output signal polarity). Beginning of the next switching cycle is determined by the external clock signal received at the CLK input. All three channels operate at a switching frequency of 1/6 of the external clock frequency and positioned 120 out-of-phase for the purpose of input and output ripple current reduction. Each channel is protected from an output short circuit condition. When an over-current condition is detected in the output switch (RSENSE1-3), the corresponding channel shuts down for 200us. HV9980 recovers automatically, when the short circuit condition is removed. Each current sense input (CS1-CS3) is equipped with a leading edge blanking delay to prevent false triggering of the current sense comparators due to circuit parasitics. Over-temperature protection is included to prevent destructive failures due to over-heating. Programmable slope compensation is available at each CS input. AGND and PGND1-3 must be tied together on the printed circuit board. VDD1-3 must be also connected together on the PCB.
Applications
LCD panel backlighting DLP RPTV or projector LED engine driver RGB decorative lighting General LED lighting
General Description
The HV9980 is a fully integrated 3-channel peak-current PWM controller for driving buck converters in constant output current mode. It is optimized for use with a large array of 20~80mA LED strings, where multiple HV9980 ICs are used sharing a common clock and a common reference voltage. Both the clock and the voltage reference are external to the HV9980 for improved output current accuracy and uniform
Typical Application Circuit
+VIN
CIN
C1 D1 L1
C2 D2 L2
C3 D3 L3
21
17
16
RREF1
1
PWMD1 PWMD2 PWMD3 CLOCK POL
4
REF1
9
CREF1
12
U1 HV9980WG
7
1
RREF2 CREF2
REF2
3
6
2
10
2
23
22
24
8
19
18
20
5 AGND
11
14
15
13
RREF3 CREF3
REF3
CDD1
1
RSENSE1
CDD2
1
2
RSENSE2
2
CDD3
3
RSENSE3
3
3
+8V
HV9980
Ordering Information
Package Option Device
15.40x7.50 body 2.65mm height (max) 1.27mm pitch
Pin Configuration
24-Lead SOW
REF1
1
24
PGND1 CS1 RSENSE1 DRAIN1 PGND2 CS2 RSENSE2 DRAIN2 DRAIN3 RSENSE3 CS3 PGND3
VDD1 CLK PWMD1 AGND POL REF2 VDD2
2
23
3
22
HV9980
-G indicates package is RoHS compliant (`Green')
HV9980WG-G
4
21
5
20
6
19
7
18
8
17
Absolute Maximum Ratings
Parameter Supply voltage, VDD Drain1-3 outputs CS1-3 inputs Other inputs and outputs Supply current, IDD Power dissipation (TA = +25C) Thermal impedance (JA) Operating ambient temperature range Operating junction temperature range Storage temperature range Value -0.3V to +10V -0.3V to +200V -0.3V to +5.0V -0.3V to VDD +10mA 1300mW 60OC/W -40C to +85C -40C to +125C1 -40C to +150C2 -65C to +150C
PWMD2 REF3 VDD3 PWMD3
9
16
10
15
11
14
12
13
24-Lead SOW
(top view)
Product Marking
Top Marking
H V 99 80WG
LLL LL LLL LL YYWW
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages referenced to ground.
Bottom Marking
CCCCCCCCCCC AAA
YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging
*May be part of top marking
Notes: 1. Operation out of this range will not guarantee electrical characteristics described in this datasheet. 2. Operation out of this range will be destructive to the IC.
24-Lead SOW (WG)
Electrical Characteristics (The specifications are at T = 25C and V
A
DD
= 8.0V, unless otherwise noted.)
Sym
Parameter * *
Min -
Typ 500 -
Max 5.3 3.0
Units V mV mA
Conditions VDD falling --Total of VDD1 - VDD3
Supply Input (VDD1 - VDD3) VDD(UVLO) VDD undervoltage threshold VDD(UVLO) IDD VDD undervoltage hysteresis Operating supply current
High Voltage Switches (DRAIN1 - RSENSE1, DRAIN2 - RSENSE2, DRAIN3 - RSENSE3) VBR Breakdown voltage * 210 V --RON ISAT On-resistance DRAIN saturation current * 200 25 45 mA IDRAIN = 50mA, VRSENSE = 0V VDRAIN = 120V, VRSENSE = 1.3V
* Denotes the specifications which apply over the full operating ambient temperature range of -40C < TA < +85C.
2
HV9980
Electrical Characteristics (cont.) (The specifications are at T = 25C and V
A DD
= 8.0V, unless otherwise noted.)
Sym VCS(LIM) TSKIP TBLANK VOS TDELAY TDELAY(LIM) FSW(max) KSW 2 3 TOFF TON VCLK,HI VCLK,LO VPWMD,HI VPWMD,LO RPWMD TOT THYST
Parameter Short circuit protection threshold Short circuit recovery delay Leading edge blanking delay Input offset voltage Propagation delay CS-to-DRAIN Shutdown delay CS-to-DRAIN Maximum switching frequency Frequency divider ratio DRAIN1-DRAIN2 phase delay DRAIN1-DRAIN3 phase delay CLK high time CLK low time CLK Input high CLK Input low PWMD Input high PWMD Input low PWMD Pull down resistance Over temperature trip limit Temperature hysteresis * * * * * * * * * -
Min 1.0 120 -7.0 500 50 50 2.0 2.0 100 125 -
Typ 200 6 120 240 200 140 60
Max 1.3 220 7.0 150 0.5 0.8 0.8 300 -
Units V s ns mV ns s kHz deg deg ns ns V V V V k C C
Conditions --------VCS - VREF = 50mV VCS = VCS(LIM) + 100mV, VREF > VCS(LIM) fCLK = 3.0MHz Guaranteed by design Guaranteed by design Guaranteed by design ------------PWMD = 5.0V Guaranteed by design Guaranteed by design
Current Sense Comparators (CS1 - REF1, CS2 - REF2, CS3 - REF3)
Oscillator Input and Frequency Divider (CLK)
PWM Dimming (PWMD1, PWMD2, PWMD3)
Over Temperature Protection
* Denotes the specifications which apply over the full operating ambient temperature range of -40C < TA < +85C.
3
HV9980
Typical Performance Characteristics (TJ = 25OC unless otherwise noted)
500 450 400 350 300 250 200 20 V DD = 6V V DD = 7V V DD = 9V
DRAIN Current (mA)
500 450 400 350 300 250 200 150 VRSENSE = 0V VRSENSE = 0.5V VRSENSE = 1V VRSENSE = 1.5V VRSENSE = 2V
DRAIN Current (mA)
V DD = 8V
VRSENSE = 3V 40 60 80 100 120 DRAIN Voltage (V) 140 160 180
40
60 100 DRAIN Voltage (V)
140
180
100 20
Output Saturation Current
(IDRAIN vs. VDRAIN at VRSENSE = 0V)
Output Saturation Current
(IDRAIN vs. VDRAIN at VDD = 8.0V)
500 450
VRSENSE = GND VRSENSE = 0.5V
DRAIN Current (mA)
500
VRSENSE = 0.8V
DRAIN Current (mA)
400 350 300 250 200 150 100 20 40 60 80
VRSENSE = 1V
460 420
VRSENSE = 2V
380 340
VRSENSE = 3V
100
120
140
160
180
DRAIN Voltage (V)
300 -40
-15
10 35 60 85 Junction Temperature (C)
110
Output Saturation Current
(IDRAIN vs. VDRAIN at VDD = 9.0V)
Output Saturation Current
(IDRAIN vs. TJ at VDD = 9.0V)
45
110.0
40 35
30
Propagation Delay (ns)
-40 -15 10 35 60 85 110
100.0
ON Resistance ()
90.0
25 20
80.0
15
Junction Temperature (C)
70.0 -40
-15
Junction Temperature (C)
10
35
60
85
110
(RON vs. TJ at VDD = 8.0 or 9.0V)
ON Resistance
CS-to-DRAIN Propagation Delay
(TDELAY vs. TJ at VDD = 8.0 or 9.0V)
4
HV9980
Typical Performance Characteristics (cont.) (TJ = 25OC unless otherwise noted)
740
280.0 250.0 220.0 190.0 160.0 130.0
Current Limit Threshold (mV)
735
730
725
Blanking Delay (ns)
720 -40
-15
Junction Temperature (C)
10
35
60
85
110
100.0 -40
-15
10
35
60
85
110
Junction Temperature (C)
Short Circuit Threshold Voltage
(VCS(LIM) vs. TJ at VDD = 8.0 or 9.0V)
Leading Edge Blanking Delay
(TBLANK vs. TJ at VDD = 8.0 or 9.0V)
Short Circuit Propagation Delay (ns)
250.0
230.0
210.0
190.0
170.0
150.0 -40
-15
Junction Temperature (C)
10
35
60
85
110
Short Circuit Protection Delay
(TDELAY(LIM) vs. TJ at VDD = 8.0 or 9.0V)
5
VIN
COM
C9 C10 C11 C12
GND CLK
D1
D2
D3
GND1 U1 5 GND POL CLK VDD1 GND1 D2 RS2 CS2 GND2 D3 RS3 CS3 GND3 14 13 15 R3 16 20 L3 19 18 R2 Ch3 17 L2 VDD2 VDD3 REF1 REF2 REF3 PWMD1 PWMD2 PWMD3 24 CS1 23 R1 Ch2 RS1 22 D1 21 L1 6 3 C3 2 8 11 1 R5 7 R6 10 C6 9 12 4 C4 C5 Ch1
VDD
C1
C2
Figure 1: 110-190VDC 3-channel 50V 70mA LED Driver Schematic
6
R4
REF
HV9980
PWMD3 PWMD2 PWMD1
HV9980
HV9980
Figure 2: 90-135VAC 3-channel 50V 70mA LED Driver Schematic
VIN
CH1
CH2
CH3
C12
C11
C10
L1
R1
L2
R2
L3
R3
D3
D2
D1
21
22
23
24
17
18
19
20
16
15
14
CS3
C15
RS1
CS1
RS2
CS2
GND1
GND2
RS3
D2
D1
D3
GND3
13
12
PW MD3
PW MD1
C14
1
7
11
10
2
5
6
3
8
4
9
PW MD2
VDD1
VDD2
VDD3
REF1
REF2
REF3
GND
PO L
CLK
HV9980
PWMD3
L4
PWMD2
C13
CLK
PWMD1
C6
R7
R6
R8
R9
RT1
VAC2
D5
D7
C5
C3
R5
C4
C2
D4
D6
R4
VDD
C1
F1
REF
VDD
VAC1
7
HV9980
Programming LED current and selecting L and D The required value of the output inductor L is inversely proportional to the ripple current IO in it. Setting the relative peak-to-peak ripple to 20~30% is a good practice to ensure noise immunity of the current sense comparator. L = (VO * TOFF) / IO = (VO * [1 - D]) / fSIO (1)
Application Information
Using an ultra-fast rectifier diode for D1 is recommended to achieve high efficiency and reduce the risk of false triggering of the current sense comparator. Using diodes with shorter reverse recovery time trr and lower junction capacitance CJ achieves better performance. The reverse voltage rating VR of the diode must be greater than the maximum input voltage of the LED lamp. The total parasitic capacitance present at the DRAIN output of the HV9980 can be calculated as: CP = CDRAIN + CPCB + CL + CJ (3)
VO is the forward voltage of the LED string, fS is the switching frequency, D = VO/VIN is the switching duty cycle. The output current in the LED string (IO) is calculated as: IO = (VREF / RSENSE) - 1/2 * IO (2)
where VREF is the voltage at REF1-3, and RSENSE is the current sense resistor at RSENSE1-3. (The ripple current introduces a peak-to-average error in the output current setting that needs to be accounted for.) Adding a filter capacitor across the LED string can reduce the output current ripple yielding a reduced value of L. However, one must keep in mind that the peak-to-average current error is affected by the variation of the input and output voltage. Therefore, the line and load regulation of the LED current might be sacrificed at large ripple current in L. Another important aspect of designing an LED driver with the HV9980 is related to certain parasitic elements of the circuit, including distributed coil capacitance of L1, junction capacitance and reverse recovery of the rectifier diode D1, capacitance of the printed circuit board traces CPCB and output capacitance CDRAIN of the controller itself. These parasitic elements affect the efficiency of the switching converter and could potentially cause false triggering of the current sense comparator if not properly managed. Minimizing these parasitics is essential for efficient and reliable operation of the HV9980. Coil capacitance of inductors is typically provided in the manufacturer's data books either directly or in terms of the self-resonant frequency (SRF). SRF = 1 / (2L * CL) where L is the inductance value, and CL is the coil capacitance.) Charging and discharging this capacitance every switching cycle causes high-current spikes in the LED string. Therefore, connecting a small capacitor CO (~10nF) is recommended to bypass these spikes.
When the switch turns on, the capacitance CP is discharged into the DRAIN output of the IC. The discharge current is limited to about 300mA typically. However, it may become lower at increased junction temperature. The duration of the leading edge current spike can be estimated as: TSPIKE = [(VIN * CP) / ISAT ] = trr (4)
In order to avoid false triggering of the current sense comparator, CP must be minimized in accordance with the following expression: CP < [ISAT * (TBLANK(MIN) - trr)] / VIN(MAX) (5)
where TBLANK(MIN) is the minimum blanking time of 120ns, and VIN(MAX) is the maximum instantaneous input voltage. Layout Considerations The HV9980 provides three independent power ground connections PGND1-3 for each channel. The PGND pins must be wired together on the printed circuit board (PCB). To minimize interference between the channels, the PGND pins should be wired to the negative terminal of the input filter capacitor CIN using separate tracks. All four power supply inputs VDD, VDD1-3 must be connected together on the PCB also. Although in many layout arrangements wiring the reference pins REF1-3 together is acceptable, further reduction of the "cross-talk" between the channels is possible by adding low-pass RC filters with the filter capacitors referenced to the corresponding PGND pins. These filters composed from RREF1-3 and CREF1-3 are shown in the Typical Application Circuit diagram.
8
HV9980
Pin Description
Pin # 1 7 10 2 8 11 3 4 9 12 5 6 13 20 24 14 19 23 15 18 22 16 17 21 Name REF1 REF2 REF3 VDD1 VDD2 VDD3 CLK PWMD1 PWMD2 PWMD3 AGND POL PGND3 PGND2 PGND1 CS3 CS2 CS1 RSENSE3 RSENSE2 RSENSE1 DRAIN3 DRAIN2 DRAIN1 Open drain outputs of the switching power MOSFETs. Common return pin for CLK, POL and PWMD inputs. Must be connected to AGND. Power return terminals for corresponding DRAIN outputs. The PGND and AGND pins must be tied together on the PCB. Signal inputs to the current sense comparators. Connect these pins to the corresponding RSENSE outputs directly when the slope compensation feature is not used. When the slope compensation is needed, connect a capacitor between each RSENSE and its corresponding CS pin, and connect a resistor between each CS pin and VDD. Open source outputs of the switching power MOSFETs. Connect a current sense resistor between each of the RSENSE pins and its corresponding PGND pin. Dedicated PWM dimming inputs for each individual LED string driver channel. Description Voltage reference inputs to the current sense comparators. For best noise immunity, connect an RC filter at each of these pins referenced to the corresponding PGND pin. The filter can consist of a 1.0nF low impedance capacitor and a 1.0k resistor. Power supply inputs. For best noise immunity, bypass each of these pins to the corresponding PGND pin with a 0.1uF low impedance capacitor. The VDD pins must be tied together on the PCB. Input to an external clock signal common to all three channels. Programs the switching frequency of the power MOSFET outputs at 1/6 of the clock signal frequency.
9
HV9980
24-Lead SOW (Wide Body) Package Outline (WG)
15.40x7.50 body, 2.65mm height (max), 1.27mm pitch
24
D
1
E1
Note 1 (Index Area 0.25D x 0.75E1) 1
E
L2
Gauge Plane
L L1
Seating Plane
Top View
A
View B
h
View B
A A2 A1 e
Seating Plane
h
Note 1
b A
Side View
View A - A
Note: 1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol Dimension NOM (mm) MAX MIN
A 2.15* 2.65
A1 0.10 0.30
A2 2.05 2.55*
b 0.31 0.51
D 15.20* 15.40
E 9.97* 10.30
E1 7.40* 7.50
e 1.27 BSC
h 0.25 0.75
L 0.40 1.27
L1 1.40 REF
L2 0.25 BSC
0O 8O
1 5O 15O
15.60* 10.63* 7.60*
JEDEC Registration MS-013, Variation AD, Issue E, Sep. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. Supertex Doc. #: DSPD-24SOWWG, Version D071408.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9980 B081808
10

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